Northrop Grumman Senior Principal Digital Verification Engineer in Morrisville, North Carolina
At the heart of Defining Possible is our commitment to missions. In rapidly changing global security environments, Northrop Grumman brings informed insights and software-secure technology to enable strategic planning. We're looking for innovators who can help us keep building on our wide portfolio of secure, affordable, integrated, and multi-domain systems and technologies that fuel those missions. By joining in our shared mission, we'll support yours of expanding your personal network and developing skills, whether you are new to the field or an industry thought-leader. At Northrop Grumman, you'll have the resources, support, and team to do some of the best work of your career.
Northrop Grumman Mission Systems, Digital Technologies Group, is seeking Digital Verification Engineers to support ASIC and FPGA product development. In this capacity, you will work closely with design and verification engineers and will utilize your knowledge of modern verification methods, tools and techniques. The individual will perform functional verification of register transfer level (RTL) code of a complex ASIC at block level and SOC level using UVM (Universal Verification Methodology) and SystemVerilog and Cadence Xcelium simulation tool. This task includes but not limited to development of testbench, tests, verification IP (VIP), verification models, coverage models, extensive simulation and debug, code coverage and functional coverage, generation and analysis of reports and metrics, documentation etc. This candidate will have an ability to operate in a team environment and collaborate across the different teams as required to accomplish the goals.
This position is located in Morrisville, NC.
Bachelor's degree in Electrical Engineering or other comparable engineering discipline
9+ years of digital verification engineering experience using industry standard simulation tools (7+ years with an MS degree; 4+ years with PhD)
Advanced Knowledge of UVM and use of a coverage-driven verification methodology
Experience developing testplans, participating in reviews, test development and RTL debug
An active DoD Security Clearance at the Secret Level (or higher)
MS in Electrical Engineering or comparable engineering discipline
Experience with data structures, object oriented programming languages and concepts
Experience with Verification IP integration and/or development
Experience with a coverage-driven verification methodology from planning through closure
Knowledge of industry standard bus or I/O interfaces
Experience with SystemVerilog Assertions (SVA)
FPGA/ASIC design and/or development process experience
Experience with scripting languages (Bash, Perl, Python, Tcl, Makefile)
Knowledge of digital signal processing
Northrop Grumman is committed to hiring and retaining a diverse workforce. We are proud to be an Equal Opportunity/Affirmative Action Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO/AA and Pay Transparency statement, please visit www.northropgrumman.com/EEO. U.S. Citizenship is required for most positions.
Job Category : Engineering